With the advent of very large scale integrated (VLSI) circuits, new levels of performance have been achieved and new types of problems have arisen. One of the most pressing concerns is design modification. If the testing of a new VLSI device reveals a performance deficit, the conventional remedy is a redesign of the device. However, successive iterations of a VLSI device incur significant cost and time liabilities. Clearly, a method of altering performance by the addition of a small, efficient external circuit would be highly preferable.
Consider the typical avionics system shown in FIG. 1. In one specific mode of operation, remote terminal VLSI (RT VLSI) device 13, after servicing Bus A 15, is commanded to service Bus B 17. The logic internal to the RT VLSI 13 device creates an "enable channel" request pulse whose duration is nearly equal to the period of a clock sampling the pulse. This often occurs in systems where a response to given stimuli must take place within a limited time. For "enable Channel A" pulses, a Channel A clock is used to sample and for "enable Channel B" pulses, a Channel B clock is used. Therefore, for successive Channel A or for successive Channel B operations, the respective pulses and clocks are synchronous. For the cases where it is desired to switch channels from A to B or B to A, the "enable channel" pulse must be latched by the clock of the presently served channel. Since the Channel A and Channel B clocks may be inherently asynchronous, it is statistically possible for the rising edges of the clock to occur close to the rising and falling edges of the "enable channel" pulse generated by the other channel. When this happens, a "set-up" or "hold" time violation of the internal logic can cause the pulse to be "missed" and the requesting channel will not be served.
Accordingly, it is desired to modify the architecture embodied in an existing circuit without changing the circuit itself. It is further desired to improve the ability of a circuit to communicate with two different communication sources in which data from the two communication sources may not be synchronous with respect to one another. It is further desired to provide data transfer and enable functions between a single circuit and two disparate data communication lines.